A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

Remco C.H. van de Beek; Cicero S. Vaucher; Domine M.W. Leenaerts; Nenad Pavlovic; Ketan Mistry; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/ISSCC.2003.1234256

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

Remco C.H. van de Beek
, Cicero S. Vaucher
, Domine M.W. Leenaerts
, Nenad Pavlovic
, Ketan Mistry
, Eric A.M. Klumperink
, Bram Nauta

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

16 Citaten (Scopus)

Samenvatting

A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

Originele taal-2	Engels
Titel	2003 IEEE International Solid-State Circuits Conference
Subtitel	Digest of Technical Papers, ISSCC
Aantal pagina's	10
DOI's	https://doi.org/10.1109/ISSCC.2003.1234256
Status	Gepubliceerd - 2003
Extern gepubliceerd	Ja
Evenement	50th IEEE International Solid-State Circuits Conference, ISSCC 2003 - San Francisco, Verenigde Staten van Amerika Duur: 9 feb. 2003 → 13 feb. 2003 Congresnummer: 50

Congres

Congres	50th IEEE International Solid-State Circuits Conference, ISSCC 2003
Verkorte titel	ISSCC 2003
Land/Regio	Verenigde Staten van Amerika
Stad	San Francisco
Periode	9/02/03 → 13/02/03

Toegang tot document

10.1109/ISSCC.2003.1234256

Andere bestanden en links

Link naar publicatie in Scopus

Citeer dit

van de Beek, R. C. H., Vaucher, C. S., Leenaerts, D. M. W., Pavlovic, N., Mistry, K., Klumperink, E. A. M., & Nauta, B. (2003). A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology. In 2003 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, ISSCC Artikel 1234256 https://doi.org/10.1109/ISSCC.2003.1234256

@inproceedings{fd253c0d3a034c299f50f1b704ff11e6,

title = "A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology",

abstract = "A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.",

author = "\{van de Beek\}, \{Remco C.H.\} and Vaucher, \{Cicero S.\} and Leenaerts, \{Domine M.W.\} and Nenad Pavlovic and Ketan Mistry and Klumperink, \{Eric A.M.\} and Bram Nauta",

year = "2003",

doi = "10.1109/ISSCC.2003.1234256",

language = "English",

isbn = "0-7803-7707-9",

booktitle = "2003 IEEE International Solid-State Circuits Conference",

note = "50th IEEE International Solid-State Circuits Conference, ISSCC 2003, ISSCC 2003 ; Conference date: 09-02-2003 Through 13-02-2003",

}

van de Beek, RCH, Vaucher, CS, Leenaerts, DMW, Pavlovic, N, Mistry, K, Klumperink, EAM & Nauta, B 2003, A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology. in 2003 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, ISSCC., 1234256, 50th IEEE International Solid-State Circuits Conference, ISSCC 2003, San Francisco, California, Verenigde Staten van Amerika, 9/02/03. https://doi.org/10.1109/ISSCC.2003.1234256

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology. / van de Beek, Remco C.H.; Vaucher, Cicero S.; Leenaerts, Domine M.W. et al.
2003 IEEE International Solid-State Circuits Conference: Digest of Technical Papers, ISSCC. 2003. 1234256.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

AU - van de Beek, Remco C.H.

AU - Vaucher, Cicero S.

AU - Leenaerts, Domine M.W.

AU - Pavlovic, Nenad

AU - Mistry, Ketan

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

N1 - Conference code: 50

PY - 2003

Y1 - 2003

N2 - A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

AB - A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

UR - https://www.scopus.com/pages/publications/0037969178

U2 - 10.1109/ISSCC.2003.1234256

DO - 10.1109/ISSCC.2003.1234256

M3 - Conference contribution

AN - SCOPUS:0037969178

SN - 0-7803-7707-9

BT - 2003 IEEE International Solid-State Circuits Conference

T2 - 50th IEEE International Solid-State Circuits Conference, ISSCC 2003

Y2 - 9 February 2003 through 13 February 2003

ER -

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18μm CMOS technology

Samenvatting

Congres

Toegang tot document

Andere bestanden en links

Vingerafdruk

Citeer dit