A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

1 Citaat (Scopus)

Uittreksel

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

TaalEngels
Titel2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's5
ISBN van elektronische versie978-1-5386-4881-0
ISBN van geprinte versie978-1-5386-4882-7
DOI's
StatusGepubliceerd - 26 apr 2018
Evenement2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italië
Duur: 27 mei 201830 mei 2018
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Congres

Congres2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Verkorte titelISCAS 2018
LandItalië
StadFlorence
Periode27/05/1830/05/18
Internet adres

Vingerafdruk

Ultra-wideband (UWB)
Modulators
Transistors
Electric power utilization
Capacitors
Networks (circuits)
Electric potential
Compensation and Redress

Trefwoorden

    Citeer dit

    Zhou, M., Neofytou, M., Bolatkale, M., Liu, Q., Zhang, C., Cenci, P., ... Breems, L. (2018). A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings [8350889] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ISCAS.2018.8350889
    Zhou, M. ; Neofytou, M. ; Bolatkale, M. ; Liu, Q. ; Zhang, C. ; Cenci, P. ; Radulov, G. ; Baltus, P. ; Breems, L./ A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018.
    @inproceedings{b800a99003e349aeacfaf379942f0983,
    title = "A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator",
    abstract = "This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.",
    keywords = "Clocks, Switches, Generators, Registers, Latches, Transistors, Power demand",
    author = "M. Zhou and M. Neofytou and M. Bolatkale and Q. Liu and C. Zhang and P. Cenci and G. Radulov and P. Baltus and L. Breems",
    year = "2018",
    month = "4",
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    language = "English",
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    Zhou, M, Neofytou, M, Bolatkale, M, Liu, Q, Zhang, C, Cenci, P, Radulov, G, Baltus, P & Breems, L 2018, A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8350889, Institute of Electrical and Electronics Engineers, Piscataway, Florence, Italië, 27/05/18. DOI: 10.1109/ISCAS.2018.8350889

    A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator. / Zhou, M.; Neofytou, M.; Bolatkale, M.; Liu, Q.; Zhang, C.; Cenci, P.; Radulov, G.; Baltus, P.; Breems, L.

    2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8350889.

    Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

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    AU - Zhou,M.

    AU - Neofytou,M.

    AU - Bolatkale,M.

    AU - Liu,Q.

    AU - Zhang,C.

    AU - Cenci,P.

    AU - Radulov,G.

    AU - Baltus,P.

    AU - Breems,L.

    PY - 2018/4/26

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    N2 - This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

    AB - This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

    KW - Clocks

    KW - Switches

    KW - Generators

    KW - Registers

    KW - Latches

    KW - Transistors

    KW - Power demand

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    M3 - Conference contribution

    SN - 978-1-5386-4882-7

    BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

    PB - Institute of Electrical and Electronics Engineers

    CY - Piscataway

    ER -

    Zhou M, Neofytou M, Bolatkale M, Liu Q, Zhang C, Cenci P et al. A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2018. 8350889. Beschikbaar vanaf, DOI: 10.1109/ISCAS.2018.8350889