A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator

M. Zhou, M. Neofytou, M. Bolatkale, Q. Liu, C. Zhang, P. Cenci, G. Radulov, P. Baltus, L. Breems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaten (Scopus)
3 Downloads (Pure)

Samenvatting

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

Originele taal-2Engels
Titel2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's5
ISBN van elektronische versie978-1-5386-4881-0
ISBN van geprinte versie978-1-5386-4882-7
DOI's
StatusGepubliceerd - 26 apr 2018
Evenement2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italië
Duur: 27 mei 201830 mei 2018
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Congres

Congres2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Verkorte titelISCAS 2018
LandItalië
StadFlorence
Periode27/05/1830/05/18
Internet adres

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