A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

M. Neofytou; M. Zhou; M. Bolatkale; Q. Liu; C. Zhang; G. Radulov; P. Baltus; L. Breems

doi:10.1109/ISCAS.2018.8351046

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

M. Neofytou, M. Zhou, M. Bolatkale, Q. Liu, C. Zhang, G. Radulov, P. Baltus, L. Breems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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Samenvatting

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4^th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

Originele taal-2	Engels
Titel	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	5
ISBN van elektronische versie	978-1-5386-4881-0
ISBN van geprinte versie	978-1-5386-4882-7
DOI's	https://doi.org/10.1109/ISCAS.2018.8351046
Status	Gepubliceerd - 26 apr 2018
Evenement	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italië Duur: 27 mei 2018 → 30 mei 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Congres

Congres	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Verkorte titel	ISCAS 2018
Land	Italië
Stad	Florence
Periode	27/05/18 → 30/05/18
Internet adres	https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

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Neofytou, M., Zhou, M., Bolatkale, M., Liu, Q., Zhang, C., Radulov, G., ... Breems, L. (2018). A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings [8351046] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2018.8351046

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abstract = "This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.",

keywords = "Modulation, Power demand, Receivers, Thermal noise, Inverters, Bandwidth, Low-frequency noise",

author = "M. Neofytou and M. Zhou and M. Bolatkale and Q. Liu and C. Zhang and G. Radulov and P. Baltus and L. Breems",

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Neofytou, M , Zhou, M, Bolatkale, M, Liu, Q , Zhang, C , Radulov, G , Baltus, P & Breems, L 2018, A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351046, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italië, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351046

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. / Neofytou, M.; Zhou, M.; Bolatkale, M.; Liu, Q.; Zhang, C.; Radulov, G.; Baltus, P.; Breems, L.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8351046.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AU - Neofytou, M.

AU - Zhou, M.

AU - Bolatkale, M.

AU - Liu, Q.

AU - Zhang, C.

AU - Radulov, G.

AU - Baltus, P.

AU - Breems, L.

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N2 - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

AB - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

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KW - Power demand

KW - Receivers

KW - Thermal noise

KW - Inverters

KW - Bandwidth

KW - Low-frequency noise

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10.1109/ISCAS.2018.8351046

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