A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

1 Citaat (Scopus)

Uittreksel

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

TaalEngels
Titel2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's5
ISBN van elektronische versie978-1-5386-4881-0
ISBN van geprinte versie978-1-5386-4882-7
DOI's
StatusGepubliceerd - 26 apr 2018
Evenement2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italië
Duur: 27 mei 201830 mei 2018
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Congres

Congres2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Verkorte titelISCAS 2018
LandItalië
StadFlorence
Periode27/05/1830/05/18
Internet adres

Vingerafdruk

Ultra-wideband (UWB)
Modulators
Bandwidth
Electric power utilization
Clock distribution networks
Transistors
Feedback

Trefwoorden

    Citeer dit

    Neofytou, M., Zhou, M., Bolatkale, M., Liu, Q., Zhang, C., Radulov, G., ... Breems, L. (2018). A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings [8351046] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ISCAS.2018.8351046
    Neofytou, M. ; Zhou, M. ; Bolatkale, M. ; Liu, Q. ; Zhang, C. ; Radulov, G. ; Baltus, P. ; Breems, L./ A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018.
    @inproceedings{0d8fdd55490c4f3fbe3fa48fed7af593,
    title = "A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications",
    abstract = "This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.",
    keywords = "Modulation, Power demand, Receivers, Thermal noise, Inverters, Bandwidth, Low-frequency noise",
    author = "M. Neofytou and M. Zhou and M. Bolatkale and Q. Liu and C. Zhang and G. Radulov and P. Baltus and L. Breems",
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    Neofytou, M, Zhou, M, Bolatkale, M, Liu, Q, Zhang, C, Radulov, G, Baltus, P & Breems, L 2018, A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351046, Institute of Electrical and Electronics Engineers, Piscataway, Florence, Italië, 27/05/18. DOI: 10.1109/ISCAS.2018.8351046

    A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. / Neofytou, M.; Zhou, M.; Bolatkale, M.; Liu, Q.; Zhang, C.; Radulov, G.; Baltus, P.; Breems, L.

    2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8351046.

    Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

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    AU - Neofytou,M.

    AU - Zhou,M.

    AU - Bolatkale,M.

    AU - Liu,Q.

    AU - Zhang,C.

    AU - Radulov,G.

    AU - Baltus,P.

    AU - Breems,L.

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    N2 - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

    AB - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

    KW - Modulation

    KW - Power demand

    KW - Receivers

    KW - Thermal noise

    KW - Inverters

    KW - Bandwidth

    KW - Low-frequency noise

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    BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

    PB - Institute of Electrical and Electronics Engineers

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    ER -

    Neofytou M, Zhou M, Bolatkale M, Liu Q, Zhang C, Radulov G et al. A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2018. 8351046. Beschikbaar vanaf, DOI: 10.1109/ISCAS.2018.8351046