Samenvatting
This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.
Originele taal-2 | Engels |
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Titel | 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings |
Plaats van productie | Piscataway |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Aantal pagina's | 5 |
ISBN van elektronische versie | 978-1-5386-4881-0 |
ISBN van geprinte versie | 978-1-5386-4882-7 |
DOI's | |
Status | Gepubliceerd - 26 apr. 2018 |
Evenement | 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) - Florence Conference Center, Florence, Italië Duur: 27 mei 2018 → 30 mei 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884 |
Congres
Congres | 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) |
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Verkorte titel | ISCAS 2018 |
Land/Regio | Italië |
Stad | Florence |
Periode | 27/05/18 → 30/05/18 |
Internet adres |