A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology

Xiaopeng Li; Yi Zhang; Zhigong Wang; Youtao Zhang; Min Zhang; Wei Cheng; Hao Gao

doi:10.1109/RFIT.2019.8929198

A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology

Xiaopeng Li, Yi Zhang, Zhigong Wang, Youtao Zhang, Min Zhang, Wei Cheng, Hao Gao

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

3 Citaten (Scopus)

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This paper describes a 14-GHz 8-bit direct digital synthesizer(DDS)which is implemented using a 0.7-μm InP double hetero-junction bipolar transistor (DHBT) process. The DDS presented uses a sin-weighted nonlinear DAC to achieve a phase-to-amplitude ROM-less architecture which can make the best of speed advantage of the InP DHBT process for medium to large scale mixed signal integrated circuits. A simplified pipelined phase accumulator is used to reduce power consumption. The average value of SFDR of the output signal of the DDS in the Nyquist bandwidth is -24.8 dBc. The circuit integrates 2122 transistors, consumes a power of 2.4-W, and has a Figure of Merit (FOM) of 5.83GHz/W.

Originele taal-2	Engels
Titel	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	3
ISBN van elektronische versie	978-1-7281-2496-4
DOI's	https://doi.org/10.1109/RFIT.2019.8929198
Status	Gepubliceerd - aug. 2019
Evenement	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) - Nanjing, China Duur: 28 aug. 2019 → 30 aug. 2019

Congres

Congres	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Land/Regio	China
Stad	Nanjing
Periode	28/08/19 → 30/08/19

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title = "A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology",

abstract = "This paper describes a 14-GHz 8-bit direct digital synthesizer(DDS)which is implemented using a 0.7-μm InP double hetero-junction bipolar transistor (DHBT) process. The DDS presented uses a sin-weighted nonlinear DAC to achieve a phase-to-amplitude ROM-less architecture which can make the best of speed advantage of the InP DHBT process for medium to large scale mixed signal integrated circuits. A simplified pipelined phase accumulator is used to reduce power consumption. The average value of SFDR of the output signal of the DDS in the Nyquist bandwidth is -24.8 dBc. The circuit integrates 2122 transistors, consumes a power of 2.4-W, and has a Figure of Merit (FOM) of 5.83GHz/W.",

author = "Xiaopeng Li and Yi Zhang and Zhigong Wang and Youtao Zhang and Min Zhang and Wei Cheng and Hao Gao",

year = "2019",

month = aug,

doi = "10.1109/RFIT.2019.8929198",

language = "English",

booktitle = "2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) ; Conference date: 28-08-2019 Through 30-08-2019",

}

Li, X, Zhang, Y, Wang, Z, Zhang, Y, Zhang, M, Cheng, W & Gao, H 2019, A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology. in 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)., 8929198, Institute of Electrical and Electronics Engineers, Piscataway, 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nanjing, China, 28/08/19. https://doi.org/10.1109/RFIT.2019.8929198

A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology. / Li, Xiaopeng; Zhang, Yi; Wang, Zhigong et al.
2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway: Institute of Electrical and Electronics Engineers, 2019. 8929198.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AU - Li, Xiaopeng

AU - Zhang, Yi

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AU - Zhang, Min

AU - Cheng, Wei

AU - Gao, Hao

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AB - This paper describes a 14-GHz 8-bit direct digital synthesizer(DDS)which is implemented using a 0.7-μm InP double hetero-junction bipolar transistor (DHBT) process. The DDS presented uses a sin-weighted nonlinear DAC to achieve a phase-to-amplitude ROM-less architecture which can make the best of speed advantage of the InP DHBT process for medium to large scale mixed signal integrated circuits. A simplified pipelined phase accumulator is used to reduce power consumption. The average value of SFDR of the output signal of the DDS in the Nyquist bandwidth is -24.8 dBc. The circuit integrates 2122 transistors, consumes a power of 2.4-W, and has a Figure of Merit (FOM) of 5.83GHz/W.

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M3 - Conference contribution

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A 14-GHz 8-bit direct digital synthesizer in InP DHBT technology

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