Samenvatting
This paper reports a 132 by 104 dynamic vision sensor (DVS) with 10μm pixel in a 65nm logic process and a synchronous address-event representation (SAER) readout capable of 180Meps throughput. The SAER architecture allows adjustable event frame rate control and supports pre-readout pixel-parallel noise and spatial redundancy suppression. The chip consumes 250μW with 100keps running at 1k event frames per second (efps), 3-5 times more power efficient than the prior art using normalized power metrics. The chip is aimed for low power IoT and real-time high-speed smart vision applications.
| Originele taal-2 | Engels |
|---|---|
| Titel | 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers |
| Uitgeverij | Institute of Electrical and Electronics Engineers |
| Pagina's | C216-C217 |
| Aantal pagina's | 2 |
| ISBN van elektronische versie | 978-4-86348-720-8 |
| ISBN van geprinte versie | 978-1-7281-0914-5 |
| DOI's | |
| Status | Gepubliceerd - 29 jul. 2019 |
| Extern gepubliceerd | Ja |
| Evenement | 2019 Symposium on VLSI Circuits - Kyoto, Japan, Kyoto, Japan Duur: 9 jun. 2019 → 14 jun. 2019 |
Congres
| Congres | 2019 Symposium on VLSI Circuits |
|---|---|
| Land/Regio | Japan |
| Stad | Kyoto |
| Periode | 9/06/19 → 14/06/19 |
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