A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using carry-save format numbers

In this paper we analyze the architecture of a 13 bits 4.096 GHz multistage decimation filter for multi-standards radio receivers. The proposed solution uses shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. It also explored the benefits of using Carry-Save format numbers over binary format number. The proposed decimation filter chain is implemented in 45 nm CMOS technology, which exploits the advantage of all architectures and exhibit the best area-power trade-off. It reduces power by 13.7%, compared with a conventional filter chain using only binary number which equals in area.