A 103-dB SFDR Calibration-Free Oversampled SAR ADC with Mismatch Error Shaping and Pre-Comparison Techniques

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 mu {W} from a single 0.8-V supply and an area of 0.033 mm2, resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- mu {W} and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.