This paper presents a baseband Frequency-Hopping Synthesizer (FHS) architecture that achieves the above requirements, along with its circuit implementation. The system uses a combination of digital techniques, such as CMOS programmable dividers for scalability, low power and robustness, and analog techniques, such as harmonics suppression and filtering, for tight control of the harmonics throughout the frequency-generation chain. The hopping generator allows the generation of 56 accurate channels with a single frequency source, making FCC compliant FHSS possible in the ISM bands (915 and 2400 MHz) at a power dissipation of only 325 muW, which is more than an order of magnitude less than existing state-of-the-art fast-hopping synthesizers. The Single-Sideband (SSB) upconversion scheme allows doubling the number of channels that can be synthesized. The synthesizer uses a single reference signal, two programmable digital dividers, a double quadrature mixer with SSB selection capability, two Walsh shapers (WS) and a final filtering stage.
|Titel||Proceedings of the IEEE International Solid-State Circuits Conference 2009, ISSCC 2009, 8-12 February 2009, San Francisco, California|
|Plaats van productie||Piscataway|
|Uitgeverij||Institute of Electrical and Electronics Engineers|
|ISBN van geprinte versie||978-1-4244-3458-9|
|Status||Gepubliceerd - 2009|
Lopelli, E., Tang, van der, J. D., Philips, K. J. P., Roermund, van, A. H. M., & Gyselinckx, B. (2009). A 0.75V 523W 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference 2009, ISSCC 2009, 8-12 February 2009, San Francisco, California (blz. 228-). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2009.4977391