A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS

Komail Badami, Kushal Dakshina Murthy, Pieter Harpe, Marian Verhelst

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

3 Citaten (Scopus)

Samenvatting

This paper reports a complete sensor-to-digital analog frontend based on a highly linear amplifier that uses a dynamic-comparator to translate voltage variations of a sensory signal to the time-domain using pulse-density-modulation, followed by a charge-pump to integrate these time-domain variations back to the voltage-domain. This, highly digital building blocks based voltage-to-time-to-voltage translation, enables a large open-loop gain proportional to the switching - frequency of the dynamic-comparator thus, enabling potential performance improvements with technology-scaling. The output of the closed-loop amplifier (50x voltage-gain) is digitized with an oversampling SAR ADC, thus allowing the complete 0.6V AFE to record a 54dB SNR along with a 0.18% THD at 75% full-scale while consuming only 1.8μW power consumption.

Originele taal-2Engels
Titel2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's241-242
Aantal pagina's2
ISBN van elektronische versie9781538667002
DOI's
StatusGepubliceerd - 25 okt 2018
Evenement32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, Verenigde Staten van Amerika
Duur: 18 jun 201822 jun 2018

Congres

Congres32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
LandVerenigde Staten van Amerika
StadHonolulu
Periode18/06/1822/06/18

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