Samenvatting
This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.
| Originele taal-2 | Engels |
|---|---|
| Artikelnummer | 9171283 |
| Pagina's (van-tot) | 322-325 |
| Aantal pagina's | 4 |
| Tijdschrift | IEEE Solid-State Circuits Letters |
| Volume | 3 |
| DOI's | |
| Status | Gepubliceerd - 2020 |
Financiering
Manuscript received May 18, 2020; revised July 11, 2020; accepted August 14, 2020. Date of publication August 19, 2020; date of current version September 11, 2020. This article was approved by Associate Editor Qiuting Huang. This work was supported by the Dutch Research Council (NWO) under Project 16594. (Corresponding author: Yuting Shen.) The authors are with the Integrated Circuits Group, Eindhoven University of Technology, 5600 MB Eindhoven, The Netherlands (e-mail: [email protected]). Digital Object Identifier 10.1109/LSSC.2020.3017874
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