A 0.32 nW-1.07 μW All-Dynamic Versatile Resistive Sensor Interface With System-Level Ratiometric Measurement

Haoming Xin (Corresponding author), Peter Baltus, Eugenio Cantatore, Pieter Harpe

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An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/ f noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/ ∘C supply and temperature sensitivity are obtained, respectively.
Originele taal-2Engels
Pagina's (van-tot)506-517
Aantal pagina's12
TijdschriftIEEE Transactions on Circuits and Systems I: Regular Papers
Nummer van het tijdschrift2
StatusGepubliceerd - 1 feb. 2022

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