A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

Georgi I. Radulov, Patrick Quinn

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review


This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units.
Originele taal-2Engels
TitelECCTD 2020 - 24th IEEE European Conference on Circuit Theory and Design
ISBN van elektronische versie9781728171838
StatusGepubliceerd - sep 2020

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