Samenvatting
This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.
Originele taal-2 | Engels |
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Titel | 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 |
Plaats van productie | Piscataway |
Uitgeverij | Institute of Electrical and Electronics Engineers |
Aantal pagina's | 4 |
ISBN van elektronische versie | 978-1-5386-2483-8 |
ISBN van geprinte versie | 978-1-5386-2484-5 |
DOI's | |
Status | Gepubliceerd - 9 mei 2018 |
Evenement | 2018 IEEE Custom Integrated Circuits Conference (CICC 2018) - San Diego, Verenigde Staten van Amerika Duur: 8 apr 2018 → 11 apr 2018 |
Congres
Congres | 2018 IEEE Custom Integrated Circuits Conference (CICC 2018) |
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Verkorte titel | CICC 2018 |
Land | Verenigde Staten van Amerika |
Stad | San Diego |
Periode | 8/04/18 → 11/04/18 |