A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

Pieter Harpe

doi:10.1109/CICC.2018.8357059

A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter

Pieter Harpe

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

3 Citaten (Scopus)

5 Downloads (Pure)

Samenvatting

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Originele taal-2	Engels
Titel	2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	4
ISBN van elektronische versie	978-1-5386-2483-8
ISBN van geprinte versie	978-1-5386-2484-5
DOI's	https://doi.org/10.1109/CICC.2018.8357059
Status	Gepubliceerd - 9 mei 2018
Evenement	2018 IEEE Custom Integrated Circuits Conference (CICC 2018) - San Diego, Verenigde Staten van Amerika Duur: 8 apr 2018 → 11 apr 2018

Congres

Congres	2018 IEEE Custom Integrated Circuits Conference (CICC 2018)
Verkorte titel	CICC 2018
Land	Verenigde Staten van Amerika
Stad	San Diego
Periode	8/04/18 → 11/04/18

Toegang tot document

10.1109/CICC.2018.8357059

Link to publication in Scopus

Vingerafdruk Duik in de onderzoeksthema's van 'A 0.0013mm<sup>2</sup> 10b 10MS/s SAR ADC with a 0.0048mm<sup>2</sup> 42dB-rejection passive FIR filter'. Samen vormen ze een unieke vingerafdruk.

Citeer dit

@inproceedings{cb8c66f89e6d4f0c992f805372739c84,

title = "A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter",

abstract = "This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.",

author = "Pieter Harpe",

year = "2018",

month = may,

day = "9",

doi = "10.1109/CICC.2018.8357059",

language = "English",

isbn = "978-1-5386-2484-5",

booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2018 IEEE Custom Integrated Circuits Conference (CICC 2018), CICC 2018 ; Conference date: 08-04-2018 Through 11-04-2018",

}

Harpe, P 2018, A 0.0013mm² 10b 10MS/s SAR ADC with a 0.0048mm² 42dB-rejection passive FIR filter. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018., 8357059, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE Custom Integrated Circuits Conference (CICC 2018), San Diego, Verenigde Staten van Amerika, 8/04/18. https://doi.org/10.1109/CICC.2018.8357059

TY - GEN

T1 - A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

AU - Harpe, Pieter

PY - 2018/5/9

Y1 - 2018/5/9

N2 - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

AB - This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

UR - http://www.scopus.com/inward/record.url?scp=85048090585&partnerID=8YFLogxK

U2 - 10.1109/CICC.2018.8357059

DO - 10.1109/CICC.2018.8357059

M3 - Conference contribution

AN - SCOPUS:85048090585

SN - 978-1-5386-2484-5

BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2018 IEEE Custom Integrated Circuits Conference (CICC 2018)

Y2 - 8 April 2018 through 11 April 2018

ER -