A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter

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3 Citaten (Scopus)
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Samenvatting

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.2μW overall in 65nm CMOS. A new DAC layout technique is used to achieve better matching without using area-expensive unit elements, resulting in a minimum ADC chip area of 36 × 36μm while achieving 9.18b ENOB. A 4× time-interleaved 15-tap passive FIR filter is implemented with switched-capacitors, realizing >42dB out-of-band rejection and 4× decimation, while occupying only 53×90μm. Both components are not only small in chip area, but also offer competitive power-efficiency.

Originele taal-2Engels
Titel2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's4
ISBN van elektronische versie978-1-5386-2483-8
ISBN van geprinte versie978-1-5386-2484-5
DOI's
StatusGepubliceerd - 9 mei 2018
Evenement2018 IEEE Custom Integrated Circuits Conference (CICC 2018) - San Diego, Verenigde Staten van Amerika
Duur: 8 apr 201811 apr 2018

Congres

Congres2018 IEEE Custom Integrated Circuits Conference (CICC 2018)
Verkorte titelCICC 2018
LandVerenigde Staten van Amerika
StadSan Diego
Periode8/04/1811/04/18

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