8T SRAM with mimicked negative bit-lines and charge limited sequential sense amplifier for wireless sensor nodes

Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

6 Citaten (Scopus)

Samenvatting

This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

Originele taal-2Engels
TitelESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
UitgeverijIEEE Computer Society
Pagina's531-534
Aantal pagina's4
ISBN van geprinte versie9781457707018
DOI's
StatusGepubliceerd - 12 dec 2011
Extern gepubliceerdJa
Evenement37th European Solid-State Circuits Conference (ESSCIRC 2011) - Finlandia Hall, Helsink, Finland
Duur: 12 sep 201116 sep 2011
Congresnummer: 37
http://www.esscirc2011.org

Congres

Congres37th European Solid-State Circuits Conference (ESSCIRC 2011)
Verkorte titelESSCIRC 2011
LandFinland
StadHelsink
Periode12/09/1116/09/11
AnderESSCIRC2011
Internet adres

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