3D design‐for‐test architecture

Erik Jan Marinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi, Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin, Brion L. Keller, Vivek Chickermane, Sandeep K. Goel

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

Samenvatting

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.
Originele taal-2Engels
TitelHandbook of 3D integration
Subtitelvolume 4: design, test, and thermal management
RedacteurenP.D. Franzon, E.J. Marinissen, M.S. Bakir
Plaats van productieWeinheim
UitgeverijWiley-VCH Verlag
Hoofdstuk12
Pagina's253-280
Aantal pagina's28
ISBN van geprinte versie978-3-527-33855-9
DOI's
StatusGepubliceerd - 8 feb 2019

Vingerafdruk Duik in de onderzoeksthema's van '3D design‐for‐test architecture'. Samen vormen ze een unieke vingerafdruk.

Citeer dit