3D design‐for‐test architecture

Erik Jan Marinissen; Mario Konijnenburg; Jouke Verbree; Chun-Chuan Chi; Sergej Deutsch; Christos Papameletis; Tobias Burgherr; Konstantin Shibin; Brion L. Keller; Vivek Chickermane; Sandeep K. Goel

doi:10.1002/9783527697052.ch12

3D design‐for‐test architecture

Erik Jan Marinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi, Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin, Brion L. Keller, Vivek Chickermane, Sandeep K. Goel

Electronic Systems

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Hoofdstuk › Academic › peer review

Samenvatting

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.

Originele taal-2	Engels
Titel	Handbook of 3D integration
Subtitel	volume 4: design, test, and thermal management
Redacteuren	P.D. Franzon, E.J. Marinissen, M.S. Bakir
Plaats van productie	Weinheim
Uitgeverij	Wiley-VCH Verlag
Hoofdstuk	12
Pagina's	253-280
Aantal pagina's	28
ISBN van geprinte versie	978-3-527-33855-9
DOI's	https://doi.org/10.1002/9783527697052.ch12
Status	Gepubliceerd - 8 feb 2019

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10.1002/9783527697052.ch12

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Citeer dit

Marinissen, E. J., Konijnenburg, M., Verbree, J., Chi, C-C., Deutsch, S., Papameletis, C., Burgherr, T., Shibin, K., Keller, B. L., Chickermane, V., & Goel, S. K. (2019). 3D design‐for‐test architecture. In P. D. Franzon, E. J. Marinissen, & M. S. Bakir (editors), Handbook of 3D integration: volume 4: design, test, and thermal management (blz. 253-280). Wiley-VCH Verlag. https://doi.org/10.1002/9783527697052.ch12

Marinissen, Erik Jan ; Konijnenburg, Mario ; Verbree, Jouke ; Chi, Chun-Chuan ; Deutsch, Sergej ; Papameletis, Christos ; Burgherr, Tobias ; Shibin, Konstantin ; Keller, Brion L. ; Chickermane, Vivek ; Goel, Sandeep K. / 3D design‐for‐test architecture. Handbook of 3D integration: volume 4: design, test, and thermal management. redacteur / P.D. Franzon ; E.J. Marinissen ; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. blz. 253-280

@inbook{76eb5b87296e4ceea868b046fcda6044,

title = "3D design‐for‐test architecture",

abstract = "IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.",

author = "Marinissen, {Erik Jan} and Mario Konijnenburg and Jouke Verbree and Chun-Chuan Chi and Sergej Deutsch and Christos Papameletis and Tobias Burgherr and Konstantin Shibin and Keller, {Brion L.} and Vivek Chickermane and Goel, {Sandeep K.}",

year = "2019",

month = feb,

day = "8",

doi = "10.1002/9783527697052.ch12",

language = "English",

isbn = "978-3-527-33855-9",

pages = "253--280",

editor = "P.D. Franzon and E.J. Marinissen and M.S. Bakir",

booktitle = "Handbook of 3D integration",

publisher = "Wiley-VCH Verlag",

address = "Germany",

}

Marinissen, EJ, Konijnenburg, M, Verbree, J, Chi, C-C, Deutsch, S, Papameletis, C, Burgherr, T, Shibin, K, Keller, BL, Chickermane, V & Goel, SK 2019, 3D design‐for‐test architecture. in PD Franzon, EJ Marinissen & MS Bakir (redactie), Handbook of 3D integration: volume 4: design, test, and thermal management. Wiley-VCH Verlag, Weinheim, blz. 253-280. https://doi.org/10.1002/9783527697052.ch12

3D design‐for‐test architecture. / Marinissen, Erik Jan; Konijnenburg, Mario; Verbree, Jouke; Chi, Chun-Chuan; Deutsch, Sergej; Papameletis, Christos; Burgherr, Tobias; Shibin, Konstantin; Keller, Brion L.; Chickermane, Vivek; Goel, Sandeep K.

Handbook of 3D integration: volume 4: design, test, and thermal management. redactie / P.D. Franzon; E.J. Marinissen; M.S. Bakir. Weinheim : Wiley-VCH Verlag, 2019. blz. 253-280.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Hoofdstuk › Academic › peer review

TY - CHAP

T1 - 3D design‐for‐test architecture

AU - Marinissen, Erik Jan

AU - Konijnenburg, Mario

AU - Verbree, Jouke

AU - Chi, Chun-Chuan

AU - Deutsch, Sergej

AU - Papameletis, Christos

AU - Burgherr, Tobias

AU - Shibin, Konstantin

AU - Keller, Brion L.

AU - Chickermane, Vivek

AU - Goel, Sandeep K.

PY - 2019/2/8

Y1 - 2019/2/8

N2 - IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.

AB - IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.

U2 - 10.1002/9783527697052.ch12

DO - 10.1002/9783527697052.ch12

M3 - Chapter

SN - 978-3-527-33855-9

SP - 253

EP - 280

BT - Handbook of 3D integration

A2 - Franzon, P.D.

A2 - Marinissen, E.J.

A2 - Bakir, M.S.

PB - Wiley-VCH Verlag

CY - Weinheim

ER -