Onderzoeksoutput per jaar
Persoonlijk profiel
Research profile
Kanishkan Vadivel is Researcher in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). His early research interest includes developing hardware architecture for energy efficient and high-performance computing, and compiler based code-generation techniques.
Kanishkan's current research includes optimal code-generation for explicit datapath architecture(CGRA) and part of MNEMOSENE project aimed to demonstrate a new computation-in-memory architecture based on resistive devices.
Quote
Designing smart and hasty machine is hard.! I take up a challenge of designing such machines with necessary tool support for usability and optimize them for energy efficiency
Academic background
Kanishkan Vadivel obtained his Master’s degree in Embedded Sytems from Eindhoven University of Technology (TU/e) in 2017 and started as a researcher in Feb 2019. Kanishkan received a bachelor degree from Coimbatore Institute of Technology(India) and has 3.5years of industrial experience in Embedded systems from Tata Engineering(India) and in Arm Ltd(Cambridge, UK).
Externe posities
Visiting Researcher, Tampere University of Technology
nov 2019 → …Vingerafdruk Verdiep u in de onderzoeksgebieden waarop Kanishkan Vadivel actief is. Deze onderwerplabels komen uit het werk van deze persoon. Samen vormen ze een unieke vingerafdruk.
- 4 Soortgelijke profielen
Netwerk
Recente externe samenwerking op landenniveau. Duik in de details door op de stippen te klikken.
Onderzoeksoutput
- 1 Citaties
- 3 Conferentiebijdrage
Towards efficient code generation for exposed datapath architectures
Vadivel, K., Jordans, R., Stuijk, S., Corporaal, H., Jääskeläinen, P. & Kultala, H., 27 mei 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (redactie). New York: Association for Computing Machinery, Inc, blz. 86-89 4 blz.Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review
Open Access
Bestand
CIM-SIM: computation in Memory SIMuIator
Banagozar, A., Wong, S., Abu Lebdeh, M., Vadivel, K., Yu, J., Hamdioui, S., Stuijk, S. & Corporaal, H., 27 mei 2019, Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019. Stuijk, S. (redactie). New York: Association for Computing Machinery, Inc, blz. 1-4 4 blz.Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review
Open Access
Bestand
1
Citaat
(Scopus)
31
Downloads
(Pure)
Loop overhead reduction techniques for coarse grained reconfigurable architectures
Vadivel, K., Wijtvliet, M., Jordans, R. & Corporaal, H., 28 sep 2017, DSD 2017 - 20th Euromicro Conference on Digital System Design, 30 August - 1 September 2017, Vienna, Austriavadivel wijtvliet jordfans. Novotny, M., Kubatova, H. & Skavhaug, A. (redactie). Piscataway: Institute of Electrical and Electronics Engineers, blz. 14-21 8 blz. 8049762Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review
Prijzen
HiPEAC collaboration grant
Kanishkan Vadivel (Ontvanger), 2019
Prijs: Anders › Fellowships & memberships › Wetenschappelijk
Scriptie
Energy efficient loop mapping techniques for coarse-grained reconfigurable architecture
Auteur: Vadivel, K., 31 aug 2017Begeleider: Corporaal, H. (Afstudeerdocent 1), Jordans, R. (Afstudeerdocent 2) & van Barkel, K. (Externe persoon) (Externe coach)
Scriptie/masterproef: Master
Bestand