CMOS scaling is approaching its physical limit and processing demands are ever increasing. To keep the energy consumption and silicon area usage within the budget, the ASIC lab focuses its research on optimizations at different levels of design stack from applications, architecture, micro-architecture, logic, circuit, device and technology.

CMOS scaling is approaching its physical limit and processing demands are ever increasing. Our aim is to design cross-stack optimizations to push the boundaries of what is physically possible.