Test time and wire length minimization for scanned IC designs : a layout-driven partitioning approach

  • M.A. Tap

Student thesis: Master

Abstract

Date of Award30 Apr 1999
Original languageEnglish
SupervisorEmile H.L. Aarts (Supervisor 1), Erik Jan Marinissen (Supervisor 2) & E.A. de Kock (Supervisor 2)

Cite this

'