Simulating based design of assembly lines in the low volume, assemble to order environment of VDL ETG

  • M. Bouman

Student thesis: Master

Date of Award30 Nov 2018
Original languageEnglish
SupervisorIvo J.B.F. Adan (Supervisor 1), Willem L. van Jaarsveld (Supervisor 2), G. van Wandeloo (External coach) & M. van Beurden (External coach)

Cite this

'