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Simulatiemodellen van SDH systemen : het beschrijven van het functioneel model van SDH in VHDL
B.F.A. Thomasse
Department of Electrical Engineering
Student thesis
:
Master
Abstract
Date of Award
15 Dec 1996
Original language
Dutch
Supervisor
M.P.J. Stevens (Supervisor 1)
Cite this
Standard
Simulatiemodellen van SDH systemen : het beschrijven van het functioneel model van SDH in VHDL
Thomasse, B. F. A. (Author).
15 Dec 1996
Student thesis
:
Master
Documents
full text
File
:
application/pdf, 5.6 MB
Type
:
Thesis