Modeling and analysis of a cache coherent interconnect

  • U. Wiener

Student thesis: Master

Date of Award31 Aug 2012
Original languageEnglish
SupervisorKees G.W. Goossens (Supervisor 1) & M.A. Hansson (Supervisor 2)

Cite this

Documents

  • full text

    File: application/pdf, 4.73 MB

    Type: Thesis

'