| Date of Award | 13 Nov 2023 |
|---|---|
| Original language | English |
| Supervisor | Georgi I. Radulov (Supervisor 1) |
Cite this
- Standard
Methodology and design of high speed, high linearity DRO/NRZ DACs in 28nm CMOS enabling a 67.8 dB DR 400 MHz FMCW CT pipeline ADC
Student thesis: Master