This work involved the study and formulation of the 3D ultrasound frontend system specifications for various blocks in order to identify the key design bottlenecks and possible opportunities for innovation for next-gen Philips Ultrasound probes. The second part of the project focused on the schematic design of a high resolution, high speed, low power SAR ADC in 65nm CMOS technology based upon the previous system level derived specifications.
|Date of Award||31 Oct 2014|
- Eindhoven University of Technology
|Supervisor||Pieter J.A. Harpe (Supervisor 1)|
- SAR ADC
- LOW POWER