An UWB, Low-power, Low-noise Quadrature VCO using a Delay Locked Loop in a 40nm CMOS Technology

Abstract

In this paper, a quadrature voltage controlled oscillator
(QVCO) is presented with delay-locked loop for ultra wideband
application. In this work, a new architecture of delay-looked
loop based QVCO is applied to achieve low power consumption
and ultra-wideband operation. In this paper, a system analysis
of delay locked loop based QVCO architecture is discussed
including the transfer function and the stability. Also, this QVCO
architecture is implemented by a 40nm CMOS technology. From
the simulated result shows, this design achieves delay range
from 6-9 GHz, with -148 dBc/Hz phase noise at 100 MHz offset
frequency. The power consumption is 11 mW, and the phase
accuracy is less then 5°.

Date of Award	29 Aug 2017
Original language	English
Awarding Institution	Electrical Engineering
Sponsors	NXP Semiconductors
Supervisor	H. Gao (Supervisor 1) & Xin He (Supervisor 1)