A converter from IDaSS 0.09 to synthesizable VHDL

  • M.N.M.A. Dassen

Student thesis: Master

Abstract

Date of Award1996
Original languageEnglish
SupervisorM.P.J. Stevens (Supervisor 1) & A.C. Verschueren (Coach)

Cite this

A converter from IDaSS 0.09 to synthesizable VHDL
Dassen, M. N. M. A. (Author). 1996

Student thesis: Master