Yield analysis for repairable embedded memories

A. Sehgal, A. Dubey, E.J. Marinissen, C. Wouters, H.P.E. Vranken, K. Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

5 Citations (Scopus)


Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.
Original languageEnglish
Title of host publicationThe Eighth IEEE European Test Workshop, 2003. Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)0-7695-1908-3
Publication statusPublished - 2003
Externally publishedYes
Event8th IEEE European Test Workshop 2003 - Crowne Plaza Hotel, Maastricht, Netherlands
Duration: 28 May 200328 May 2003
Conference number: 8


Conference8th IEEE European Test Workshop 2003
Abbreviated titleETW'03
Internet address


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