Yield analysis for repairable embedded memories

A. Sehgal; A. Dubey; E.J. Marinissen; C. Wouters; H.P.E. Vranken; K. Chakrabarty

doi:10.1109/ETW.2003.1231666

Yield analysis for repairable embedded memories

A. Sehgal, A. Dubey, E.J. Marinissen, C. Wouters, H.P.E. Vranken, K. Chakrabarty

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

Abstract

Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.

Original language	English
Title of host publication	Proceedings - 8th IEEE European Test Workshop, ETW 2003
Publisher	Institute of Electrical and Electronics Engineers
Pages	35-40
Number of pages	6
ISBN (Electronic)	0769519083
ISBN (Print)	0-7695-1908-3
DOIs	https://doi.org/10.1109/ETW.2003.1231666
Publication status	Published - 2003
Externally published	Yes
Event	8th IEEE European Test Workshop, ETW 2003 - Crowne Plaza Hotel, Maastricht, Netherlands Duration: 25 May 2003 → 28 May 2003 Conference number: 8 http://www.ieee-ets.org/past_events/etw03/

Conference

Conference	8th IEEE European Test Workshop, ETW 2003
Abbreviated title	ETW'03
Country/Territory	Netherlands
City	Maastricht
Period	25/05/03 → 28/05/03
Internet address	http://www.ieee-ets.org/past_events/etw03/

Keywords

Algorithm design and analysis
Automatic testing
Circuit faults
Circuit testing
Heuristic algorithms
Manufacturing industries
Partitioning algorithms
Redundancy
Silicon
Very large scale integration

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10.1109/ETW.2003.1231666

Cite this

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title = "Yield analysis for repairable embedded memories",

abstract = "Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.",

keywords = "Algorithm design and analysis, Automatic testing, Circuit faults, Circuit testing, Heuristic algorithms, Manufacturing industries, Partitioning algorithms, Redundancy, Silicon, Very large scale integration",

author = "A. Sehgal and A. Dubey and E.J. Marinissen and C. Wouters and H.P.E. Vranken and K. Chakrabarty",

year = "2003",

doi = "10.1109/ETW.2003.1231666",

language = "English",

isbn = "0-7695-1908-3",

pages = "35--40",

booktitle = "Proceedings - 8th IEEE European Test Workshop, ETW 2003",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "8th IEEE European Test Workshop, ETW 2003, ETW'03 ; Conference date: 25-05-2003 Through 28-05-2003",

url = "http://www.ieee-ets.org/past_events/etw03/",

}

Sehgal, A, Dubey, A, Marinissen, EJ, Wouters, C, Vranken, HPE & Chakrabarty, K 2003, Yield analysis for repairable embedded memories. in Proceedings - 8th IEEE European Test Workshop, ETW 2003., 1231666, Institute of Electrical and Electronics Engineers, pp. 35-40, 8th IEEE European Test Workshop, ETW 2003, Maastricht, Netherlands, 25/05/03. https://doi.org/10.1109/ETW.2003.1231666

TY - GEN

T1 - Yield analysis for repairable embedded memories

AU - Sehgal, A.

AU - Dubey, A.

AU - Marinissen, E.J.

AU - Wouters, C.

AU - Vranken, H.P.E.

AU - Chakrabarty, K.

N1 - Conference code: 8

PY - 2003

Y1 - 2003

N2 - Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.

AB - Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.

KW - Algorithm design and analysis

KW - Automatic testing

KW - Circuit faults

KW - Circuit testing

KW - Heuristic algorithms

KW - Manufacturing industries

KW - Partitioning algorithms

KW - Redundancy

KW - Silicon

KW - Very large scale integration

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U2 - 10.1109/ETW.2003.1231666

DO - 10.1109/ETW.2003.1231666

M3 - Conference contribution

SN - 0-7695-1908-3

SP - 35

EP - 40

BT - Proceedings - 8th IEEE European Test Workshop, ETW 2003

PB - Institute of Electrical and Electronics Engineers

T2 - 8th IEEE European Test Workshop, ETW 2003

Y2 - 25 May 2003 through 28 May 2003

ER -

Yield analysis for repairable embedded memories

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Keywords

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