X: a comprehensive analytic model for parallel machines

A. Li, S.L. Song, E. Brugel, A. Kumar, D. Chavarria-Miranda, H. Corporaal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

10 Citations (Scopus)

Abstract

To continuously comply with Moore's Law, modern parallel machines become increasingly complex. Effectively tuning application performance for these machines therefore becomes a daunting task. Moreover, identifying performance bottlenecks at application and architecture level, as well as evaluating various optimization strategies, are becoming extremely difficult when the entanglement of numerous correlated factors is being presented. To tackle these challenges, we present a visual analytical model named "X". It is intuitive and sufficiently flexible to track all the typical features of a parallel machine. Different from the conventional analytic models that focus on the temporal state of a representative core or thread, our proposed X-model concentrates on the spatial state of the parallel machines - the distribution of concurrent threads among different subsystems of these machines, while predicting the overall throughput based on such state. One major highlight of our model is its tractability as it only requires a small number of essential parameters from the application and architecture. Meanwhile, it is able to effectively help users investigate the combined-effects of different types of parallelism: the instruction-level-parallelism (ILP), the thread-level-parallelism (TLP), the memory-level-parallelism (MLP) and the data-level-parallelism (DLP). Through the X-model, developers and architects can quickly draw an intuitive figure called X-graph to identify performance bottlenecks and play "what-if " scenarios to evaluate the effectiveness of the proposed optimization techniques by investigating their individual and combined effects.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016, 23-27 May 2016, Chicago, Illinois
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages242-252
Number of pages11
ISBN (Electronic)978-1-5090-2140-6
ISBN (Print)978-1-5090-2141-3
DOIs
Publication statusPublished - 18 Jul 2016
Event30th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016) - Chicago, United States
Duration: 23 May 201627 May 2016
Conference number: 30

Conference

Conference30th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016)
Abbreviated titleIPDPS 2016
CountryUnited States
CityChicago
Period23/05/1627/05/16

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