Wrapper design for the reuse of networks-on-chip as test access mechanism

A.M. Amory, K.G.W. Goossens, E.J. Marinissen, M. Lubaszewski, F. Moraes

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

35 Citations (Scopus)


This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Æthereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM. © 2006 IEEE.
Original languageEnglish
Title of host publication11th IEEE European Test Symposium, ETS 2006, 21 May 2006 through 21 May 2006, Southampton
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)0-7695-2566-0
Publication statusPublished - 2006
Event11th IEEE European Test Symposium (ETS 2006) - Southampton, United Kingdom
Duration: 21 May 200625 May 2006
Conference number: 11


Conference11th IEEE European Test Symposium (ETS 2006)
Abbreviated titleETS 2006
CountryUnited Kingdom
OtherIEEE European Test Symposium, Southampton, UK
Internet address

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