Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

A.M. Amory, K.G.W. Goossens, Erik Jan Marinissen, M. Lubaszewski, F. Moraes

Research output: Contribution to journalArticleAcademicpeer-review

32 Citations (Scopus)
1 Downloads (Pure)


A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated test access mechanism (TAM), such as a TestRail or test bus. The approach leaves both the tester, as well as the embedded core and its test unchanged, while the functional interconnect can handle the test data transport as a regular data application. The functional interconnect is required to offer guaranteed throughput and zero latency variation, a service that is available in many buses and networks. For 672 example cases based on the ITC'02 System-on-Chip (SOC) Test Benchmarks, the new approach in comparison with the conventional approach shows an average wrapper area increase of 14.5, which is negligible at the SOC level, especially since the dedicated TAM can be eliminated. Futhermore, the new approach decreases the core test length by 3.8 on average. © The Institution of Engineering and Technology 2007. U7 - Cited By (since 1996): 10 U7 - Export Date: 5 February 2010 U7 - Source: Scopus
Original languageEnglish
Pages (from-to)197-206
JournalIET Computers and Digital Techniques
Issue number3
Publication statusPublished - 2007


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