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Ultracompact optical submodules for parallel optical interconnects are demonstrated based on a three-level silicon interposer, which is fabricated through a low-cost wet etching process. Using three steps of wet etching of silicon, a multilevel cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through-silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50- μ m thermal isolation air gap is formed between dies as a part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness. Based on this 3-D packaging concept, compact 4 mm ×6 mm, 10-Gb/s 12-channel transmitter and receiver submodules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 and 15 Gb/s for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver submodules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10 -12. Also, crosstalk for both modules is tested, yielding only a 0.1- and 0.8-dB additional penalty for transmitter and receiver, respectively.
|Number of pages||8|
|Journal||IEEE Transactions on Components, Packaging and Manufacturing Technology|
|Publication status||Published - Apr 2018|
- Flip chip
- heterogeneous integration
- Optical interconnects
- thermal isolation
- silicon interposer
- optical interconnects
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- 1 Active
Zwaartekracht ECO Research Centre for Integrated Nanophotonics
Koonen, A. M. J., van Zantvoort, J. H. C., Smit, M., Cao, Z., van der Heide, S., Shi, B., Spiegelberg, M., Raz, O., Al-Daffaie, S., Mukit, M., Shi, B., Lei, Y. & Spiegelberg, M.
1/01/14 → 31/12/23
Project: Research direct