Wet etched 3-level silicon interposer for 3 dimensional embedding and connecting of opto-electronic dies and CMOS ICs

C. Li, R. Stabile, T. Li, E. Smalbrugge, G. Guelbenzu de Villota, O. Raz

Research output: Contribution to journalArticleAcademicpeer-review

3 Citations (Scopus)
123 Downloads (Pure)

Abstract

Ultra-compact optical sub-modules for parallel optical interconnects are demonstrated based on a 3-level silicon interposer, which is fabricated through a low cost wet etching process. Using three steps of wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50 μm thermal isolation air gap is formed between dies as part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness.
Based on this 3D packaging concept, compact 4 mm × 6 mm, 10 Gbps 12-channel transmitter and receiver sub-modules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 Gbps and 15 Gbps for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver sub-modules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10-12. Also, crosstalk for both modules is tested, yielding only a 0.1 dB and 0.8 dB additional penalty for transmitter and receiver respectively.
Original languageEnglish
Pages (from-to)570-577
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Volume8
Issue number4
DOIs
Publication statusPublished - 28 Jan 2018

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Silicon
Bit error rate
Transmitters
Wet etching
Naphazoline
Optical interconnects
Crosstalk
Packaging
Testing
Air
Hot Temperature
Costs
Experiments

Keywords

  • Flip chip
  • heterogeneous integration
  • Optical interconnects
  • thermal isolation
  • silicon interposer

Cite this

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title = "Wet etched 3-level silicon interposer for 3 dimensional embedding and connecting of opto-electronic dies and CMOS ICs",
abstract = "Ultra-compact optical sub-modules for parallel optical interconnects are demonstrated based on a 3-level silicon interposer, which is fabricated through a low cost wet etching process. Using three steps of wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50 μm thermal isolation air gap is formed between dies as part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness.Based on this 3D packaging concept, compact 4 mm × 6 mm, 10 Gbps 12-channel transmitter and receiver sub-modules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 Gbps and 15 Gbps for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver sub-modules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10-12. Also, crosstalk for both modules is tested, yielding only a 0.1 dB and 0.8 dB additional penalty for transmitter and receiver respectively.",
keywords = "Flip chip, heterogeneous integration, Optical interconnects, thermal isolation, silicon interposer",
author = "C. Li and R. Stabile and T. Li and E. Smalbrugge and {Guelbenzu de Villota}, G. and O. Raz",
year = "2018",
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doi = "10.1109/TCPMT.2017.2786550",
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Wet etched 3-level silicon interposer for 3 dimensional embedding and connecting of opto-electronic dies and CMOS ICs. / Li, C.; Stabile, R.; Li, T.; Smalbrugge, E.; Guelbenzu de Villota, G.; Raz, O.

In: IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 8, No. 4, 28.01.2018, p. 570-577.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - Wet etched 3-level silicon interposer for 3 dimensional embedding and connecting of opto-electronic dies and CMOS ICs

AU - Li, C.

AU - Stabile, R.

AU - Li, T.

AU - Smalbrugge, E.

AU - Guelbenzu de Villota, G.

AU - Raz, O.

PY - 2018/1/28

Y1 - 2018/1/28

N2 - Ultra-compact optical sub-modules for parallel optical interconnects are demonstrated based on a 3-level silicon interposer, which is fabricated through a low cost wet etching process. Using three steps of wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50 μm thermal isolation air gap is formed between dies as part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness.Based on this 3D packaging concept, compact 4 mm × 6 mm, 10 Gbps 12-channel transmitter and receiver sub-modules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 Gbps and 15 Gbps for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver sub-modules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10-12. Also, crosstalk for both modules is tested, yielding only a 0.1 dB and 0.8 dB additional penalty for transmitter and receiver respectively.

AB - Ultra-compact optical sub-modules for parallel optical interconnects are demonstrated based on a 3-level silicon interposer, which is fabricated through a low cost wet etching process. Using three steps of wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping optical and electrical dies, and opening optical through silicon vias. In order to reduce thermal coupling between CMOS and GaAs dies, a 50 μm thermal isolation air gap is formed between dies as part of the assembly concept, and thermal simulations and experiments are carried to validate its effectiveness.Based on this 3D packaging concept, compact 4 mm × 6 mm, 10 Gbps 12-channel transmitter and receiver sub-modules are fully assembled and tested. Clear and uniform eye patterns for both modules are captured at 10 Gbps and 15 Gbps for every channel. Bit error rate (BER) testing is also performed. Both transmitter and receiver sub-modules show uniform BER curves, with receiver sensitivity spreading less than 1 dB at a BER lower than 10-12. Also, crosstalk for both modules is tested, yielding only a 0.1 dB and 0.8 dB additional penalty for transmitter and receiver respectively.

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