Vt balancing and device sizing towards high yield of sub-threshold static logic gates

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Original languageEnglish
Title of host publicationProc. of International Symposium on Low Power Electronics and Design
Place of PublicationPortland, USA
Pages355-358
Publication statusPublished - 2007
Eventconference; International Syposium on Low Power Electronics and Design 2007 -
Duration: 1 Jan 2007 → …

Conference

Conferenceconference; International Syposium on Low Power Electronics and Design 2007
Period1/01/07 → …
OtherInternational Syposium on Low Power Electronics and Design 2007

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