Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

Kamlesh Singh; Barry de Bruin; Jos Huisken; Hailong Jiao; Jose Pineda de Gyvez

doi:10.1109/SOCC46988.2019.1570558508

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, Jose Pineda de Gyvez

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.

Original language	English
Title of host publication	Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
Editors	Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
Publisher	IEEE Computer Society
Pages	370-375
Number of pages	6
ISBN (Electronic)	9781728134826
DOIs	https://doi.org/10.1109/SOCC46988.2019.1570558508
Publication status	Published - Sept 2019
Event	32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore Duration: 3 Sept 2019 → 6 Sept 2019

Conference

Conference	32nd IEEE International System on Chip Conference, SOCC 2019
Country/Territory	Singapore
City	Singapore
Period	3/09/19 → 6/09/19

Keywords

charge recycling
current sink
level shifter
near/sub-threshold
Power domain
voltage regulator

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/SOCC46988.2019.1570558508

Cite this

Singh, K., de Bruin, B., Huisken, J., Jiao, H., & de Gyvez, J. P. (2019). Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. In D. Zhao, A. Basu, M. Bayoumi, G. B. Hwee, G. Tong, & R. Sridhar (Eds.), Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019 (pp. 370-375). Article 9088006 IEEE Computer Society. https://doi.org/10.1109/SOCC46988.2019.1570558508

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title = "Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation",

abstract = "Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.",

keywords = "charge recycling, current sink, level shifter, near/sub-threshold, Power domain, voltage regulator",

author = "Kamlesh Singh and {de Bruin}, Barry and Jos Huisken and Hailong Jiao and {de Gyvez}, {Jose Pineda}",

year = "2019",

month = sep,

doi = "10.1109/SOCC46988.2019.1570558508",

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editor = "Danella Zhao and Arindam Basu and Magdy Bayoumi and Hwee, {Gwee Bah} and Ge Tong and Ramalingam Sridhar",

booktitle = "Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019",

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note = "32nd IEEE International System on Chip Conference, SOCC 2019 ; Conference date: 03-09-2019 Through 06-09-2019",

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Singh, K, de Bruin, B, Huisken, J, Jiao, H & de Gyvez, JP 2019, Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. in D Zhao, A Basu, M Bayoumi, GB Hwee, G Tong & R Sridhar (eds), Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019., 9088006, IEEE Computer Society, pp. 370-375, 32nd IEEE International System on Chip Conference, SOCC 2019, Singapore, Singapore, 3/09/19. https://doi.org/10.1109/SOCC46988.2019.1570558508

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. / Singh, Kamlesh; de Bruin, Barry; Huisken, Jos et al.
Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019. ed. / Danella Zhao; Arindam Basu; Magdy Bayoumi; Gwee Bah Hwee; Ge Tong; Ramalingam Sridhar. IEEE Computer Society, 2019. p. 370-375 9088006.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - de Gyvez, Jose Pineda

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N2 - Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.

AB - Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.

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KW - current sink

KW - level shifter

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KW - Power domain

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A2 - Basu, Arindam

A2 - Bayoumi, Magdy

A2 - Hwee, Gwee Bah

A2 - Tong, Ge

A2 - Sridhar, Ramalingam

PB - IEEE Computer Society

T2 - 32nd IEEE International System on Chip Conference, SOCC 2019

Y2 - 3 September 2019 through 6 September 2019

ER -

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

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Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

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Keywords

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