Systems on chip (SOC) contain multiple concurrent applicationswith different time criticality (firm, soft, non real-time). As aresult, they are often developed by different teams or companies, withdifferent models of computation (MOC) such as dataflow, Kahn processnetworks (KPN), or time-triggered (TT). SOC functionality and (realtime)performance is verified after all applications have been integrated.In this paper we propose the CompSOC platform and design flows thatoffers a virtual execution platform per application, to allow independentdesign, verification, and execution. We introduce the composability andpredictability concepts, why they help, and how they are implemented inthe different resources of the CompSOC architecture. We define a designflow that allows real-time cyclo-static dataflow (CSDF) applications to beautomatically mapped, verified, and executed. Mapping and analysis ofKPN and TT applications is not automated but they do run composablyin their allocated virtual platforms.Although most of the techniques used here have been publishedin isolation, this paper is the first comprehensive overview of theCompSOC approach. Moreover, three new case studies illustrate allclaimed benefits: 1) An example firm-real-time CSDF H.263 decoderis automatically mapped and verified. 2) Applications with differentmodels of computation (CSDF and TT) run composably. 3) Adaptivesoft-real-time applications execute composably and can hence be verifiedindependently by simulation.
|Title of host publication||Proceedings of the 5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, 4 December 2012, San Juan, Puerto Rico|
|Publication status||Published - 2012|
|Event||conference; CRTS 2012; 2012-12-04; 2012-12-04 - |
Duration: 4 Dec 2012 → 4 Dec 2012
|Conference||conference; CRTS 2012; 2012-12-04; 2012-12-04|
|Period||4/12/12 → 4/12/12|