Virtual design and qualification of IC backend structures

R.B.R. Silfhout, van, O. Sluis, van der, W.D. Driel, van, J.H.J. Janssen, G.Q. Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)


For Integrated Circuit (IC) wafer backend development, process developers have to design robust backend structures that guarantee both functionality and reliability during waferfab processes, packaging, qualification tests and lifetime. Figure 1 shows a simplified diagram for the design (and redesign) cycle forevelopment. Subsequently, package development IC development. Subsequently, package develop t . inherited runs a similar cycle. By using reliability modell relate it to the interaction of IC and package assembly, such as IC/compound delamination, we aim at integrating IC and packge prototyping in order to develop reliable IC packages faster. This paper presents parts of our research to approach thermo-mechanical IC reliability by virtually designing and quaifying IC backend structures in both IC processing, packaging and testing processes. By combining experimental and numerical results, targeted failure modes and mechanisms as well as their interactions are understood. It is found that delamination is the key trigger for passivation cracking and metal shift. Even more, the layout of interconnect metals in the backend of ICs has a major effect on under bond-pad wir delamination observed after wafer probing an wire ing. Reliable predictive modelling approaches enable IC package development towards a first-time-right practice.
Original languageEnglish
Title of host publicationProceedings of 7th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems (EuroSimE 2006), 24-26 April 2006, Como, Italy
Place of PublicationItaly, Como
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)1-4244-0275-1
Publication statusPublished - 2006


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