Very wide register : an asymmetric register file organization for low power embedded processors.

P. Raghavan; A. Lambrechts; M. Jayapala; F. Catthoor; D.T.M.L. Verkest; H. Corporaal

doi:10.1145/1266366.1266596

Very wide register : an asymmetric register file organization for low power embedded processors.

P. Raghavan, A. Lambrechts, M. Jayapala, F. Catthoor, D.T.M.L. Verkest, H. Corporaal

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

19 Citations (Scopus)

Abstract

In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from Software Defined Radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of upto 10X with respect to conventional multi-ported register file over the different benchmarks.

Original language	English
Title of host publication	Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007
Place of Publication	Nice
Publisher	IEEE Computer Society
Pages	1066-1071
ISBN (Print)	978-3-9810801-2-4
DOIs	https://doi.org/10.1145/1266366.1266596
Publication status	Published - 2007
Event	10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) - Acropolis, Nice, France Duration: 16 Apr 2007 → 20 Apr 2007 Conference number: 10

Conference

Conference	10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007)
Abbreviated title	DATE 2007
Country/Territory	France
City	Nice
Period	16/04/07 → 20/04/07

Access to Document

10.1145/1266366.1266596

Cite this

Raghavan, P., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D. T. M. L., & Corporaal, H. (2007). Very wide register : an asymmetric register file organization for low power embedded processors. In Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007 (pp. 1066-1071). IEEE Computer Society. https://doi.org/10.1145/1266366.1266596

@inproceedings{b06c04c21a0d4e62afe60f625092ed8c,

title = "Very wide register : an asymmetric register file organization for low power embedded processors.",

abstract = "In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from Software Defined Radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of upto 10X with respect to conventional multi-ported register file over the different benchmarks.",

author = "P. Raghavan and A. Lambrechts and M. Jayapala and F. Catthoor and D.T.M.L. Verkest and H. Corporaal",

year = "2007",

doi = "10.1145/1266366.1266596",

language = "English",

isbn = "978-3-9810801-2-4",

pages = "1066--1071",

booktitle = "Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007",

publisher = "IEEE Computer Society",

address = "United States",

note = "10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), DATE 2007 ; Conference date: 16-04-2007 Through 20-04-2007",

}

Raghavan, P, Lambrechts, A, Jayapala, M, Catthoor, F, Verkest, DTML & Corporaal, H 2007, Very wide register : an asymmetric register file organization for low power embedded processors. in Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007. IEEE Computer Society, Nice, pp. 1066-1071, 10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice, France, 16/04/07. https://doi.org/10.1145/1266366.1266596

Very wide register : an asymmetric register file organization for low power embedded processors. / Raghavan, P.; Lambrechts, A.; Jayapala, M. et al.
Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007. Nice: IEEE Computer Society, 2007. p. 1066-1071.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Very wide register : an asymmetric register file organization for low power embedded processors.

AU - Raghavan, P.

AU - Lambrechts, A.

AU - Jayapala, M.

AU - Catthoor, F.

AU - Verkest, D.T.M.L.

AU - Corporaal, H.

N1 - Conference code: 10

PY - 2007

Y1 - 2007

N2 - In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from Software Defined Radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of upto 10X with respect to conventional multi-ported register file over the different benchmarks.

AB - In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the datapath. Several realistic kernels from the TI DSP benchmark and from Software Defined Radio (SDR) are mapped on the architecture. A complete physical design of the architecture is done in TSMC 90nm technology. The novel architecture presented is shown to obtain energy gains of upto 10X with respect to conventional multi-ported register file over the different benchmarks.

UR - http://doi.acm.org/10.1145/1266366.1266596

U2 - 10.1145/1266366.1266596

DO - 10.1145/1266366.1266596

M3 - Conference contribution

SN - 978-3-9810801-2-4

SP - 1066

EP - 1071

BT - Proc. of Design Automation and Test in Europe 2007 (DATE 2007), Nice, France, 19-20 April 2007

PB - IEEE Computer Society

CY - Nice

T2 - 10th Design, Automation and Test in Europe Conference and Exhibition (DATE 2007)

Y2 - 16 April 2007 through 20 April 2007

ER -

Very wide register : an asymmetric register file organization for low power embedded processors.

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this