Vectorization of Reed Solomon decoding and mapping on the EVP

A. Kumar; C.H. Berkel, van

doi:10.1109/DATE.2008.4484722

Vectorization of Reed Solomon decoding and mapping on the EVP

A. Kumar, C.H. Berkel, van

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

2 Downloads (Pure)

Abstract

Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-throughput RS decoding on vector DSPs. The four modules of such a decoder, viz. Syndrome Computation, Key Equation Solver, Chien Search, and Forney pose different vectorization challenges. Their vectorizations are explained in detail, including optimizations speci??c for EmbeddedV etor Processor (EVP). For RS (255,239), this solution is benchmarked vs published implementations, and scalability up to vector size 64 is explored. The best and the worst case throughput of our implementation is 8 times and 2 times higher respectively than other architectures.

Original language	English
Title of host publication	Proceedings 11th Design, Automation and Test in Europe - Conference and Exhibition (DATE'08, Munich, Germany, March 10-14, 2008)
Place of Publication	Leuven
Publisher	EDAA
Pages	450-455
ISBN (Print)	978-3-9810801-4-8
DOIs	https://doi.org/10.1109/DATE.2008.4484722
Publication status	Published - 2008

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title = "Vectorization of Reed Solomon decoding and mapping on the EVP",

abstract = "Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-throughput RS decoding on vector DSPs. The four modules of such a decoder, viz. Syndrome Computation, Key Equation Solver, Chien Search, and Forney pose different vectorization challenges. Their vectorizations are explained in detail, including optimizations speci??c for EmbeddedV etor Processor (EVP). For RS (255,239), this solution is benchmarked vs published implementations, and scalability up to vector size 64 is explored. The best and the worst case throughput of our implementation is 8 times and 2 times higher respectively than other architectures.",

author = "A. Kumar and {Berkel, van}, C.H.",

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doi = "10.1109/DATE.2008.4484722",

language = "English",

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Vectorization of Reed Solomon decoding and mapping on the EVP. / Kumar, A.; Berkel, van, C.H.
Proceedings 11th Design, Automation and Test in Europe - Conference and Exhibition (DATE'08, Munich, Germany, March 10-14, 2008). Leuven: EDAA, 2008. p. 450-455.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

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AU - Kumar, A.

AU - Berkel, van, C.H.

PY - 2008

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N2 - Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-throughput RS decoding on vector DSPs. The four modules of such a decoder, viz. Syndrome Computation, Key Equation Solver, Chien Search, and Forney pose different vectorization challenges. Their vectorizations are explained in detail, including optimizations speci??c for EmbeddedV etor Processor (EVP). For RS (255,239), this solution is benchmarked vs published implementations, and scalability up to vector size 64 is explored. The best and the worst case throughput of our implementation is 8 times and 2 times higher respectively than other architectures.

AB - Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-throughput RS decoding on vector DSPs. The four modules of such a decoder, viz. Syndrome Computation, Key Equation Solver, Chien Search, and Forney pose different vectorization challenges. Their vectorizations are explained in detail, including optimizations speci??c for EmbeddedV etor Processor (EVP). For RS (255,239), this solution is benchmarked vs published implementations, and scalability up to vector size 64 is explored. The best and the worst case throughput of our implementation is 8 times and 2 times higher respectively than other architectures.

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DO - 10.1109/DATE.2008.4484722

M3 - Conference contribution

SN - 978-3-9810801-4-8

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BT - Proceedings 11th Design, Automation and Test in Europe - Conference and Exhibition (DATE'08, Munich, Germany, March 10-14, 2008)

PB - EDAA

CY - Leuven

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Vectorization of Reed Solomon decoding and mapping on the EVP

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