Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode

H. Jiao; Y. Qiu; V. Kursun

doi:10.1109/IOLTS.2016.7604668

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode

H. Jiao
, Y. Qiu
, V. Kursun

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

Abstract

Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

Original language	English
Title of host publication	2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4-6 July 2016,
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	39-42
Number of pages	4
ISBN (Electronic)	978-1-5090-1507-8
ISBN (Print)	978-1-5090-1508-5
DOIs	https://doi.org/10.1109/IOLTS.2016.7604668
Publication status	Published - 20 Oct 2016
Event	22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 - Sant Feliu de Guixols, Catalunya, Spain Duration: 4 Jul 2016 → 6 Jul 2016

Conference

Conference	22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
Country/Territory	Spain
City	Sant Feliu de Guixols, Catalunya
Period	4/07/16 → 6/07/16

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10.1109/IOLTS.2016.7604668

Cite this

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title = "Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode",

abstract = "Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84\%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78\% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.",

author = "H. Jiao and Y. Qiu and V. Kursun",

year = "2016",

month = oct,

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doi = "10.1109/IOLTS.2016.7604668",

language = "English",

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pages = "39--42",

booktitle = "2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4-6 July 2016,",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 ; Conference date: 04-07-2016 Through 06-07-2016",

}

Jiao, H, Qiu, Y & Kursun, V 2016, Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. in 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4-6 July 2016,., 7604668, Institute of Electrical and Electronics Engineers, Piscataway, pp. 39-42, 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Catalunya, Spain, 4/07/16. https://doi.org/10.1109/IOLTS.2016.7604668

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. / Jiao, H.; Qiu, Y.; Kursun, V.
2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4-6 July 2016,. Piscataway: Institute of Electrical and Electronics Engineers, 2016. p. 39-42 7604668.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode

AU - Jiao, H.

AU - Qiu, Y.

AU - Kursun, V.

PY - 2016/10/20

Y1 - 2016/10/20

N2 - Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

AB - Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

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DO - 10.1109/IOLTS.2016.7604668

M3 - Conference contribution

AN - SCOPUS:84997078111

SN - 978-1-5090-1508-5

SP - 39

EP - 42

BT - 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, 4-6 July 2016,

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016

Y2 - 4 July 2016 through 6 July 2016

ER -

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode

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