Using transport triggered architectures for embedded processor design

In this paper we propose the usage of Transport Triggered Architectures (TTAs) as a template for the design of application specific processors. TTAs can be compared to VLIWs (Very Long Instruction Word processors); both exploit the instruction level parallelism available at compile-time. However, TTAs are programmed differently. TTAs combine a set of interesting features; apart from being fully programmable, they have favorable scaling characteristics, they easily incorporate arbitrary functionality, and their organization is well structured, allowing easy and automatic design. The paper explains these features. Based on this template a set of design tools has been developed; they include a parallelizing C/C++ compiler which exploits the available processor and application concurrency, aprocessor generator, simulators, profilers, and a tool for architecture exploration; these tools are integrated within a graphical user interface. In the paper we briefly describe these tools and demonstrate how they can be applied to a particular application. This example application is taken from the image processing area. It will be shown how the tools assist in exploring many solutions, including those which incorporate application specific functionality