Abstract
Unrolling a decoding algorithm allows to achieve extremely high throughput at the cost of increased area. Lookup tables (LUTs) can be used to replace functions otherwise implemented as circuits. In this work, we show the impact of replacing blocks of logic by carefully crafted LUTs in unrolled decoders for polar codes. We show that using LUTs to improve key performance metrics (e.g., area, throughput, latency) may turn out more challenging than expected. We present three variants of LUT-based decoders and describe their inner workings as well as circuits in detail. The LUT-based decoders are compared against a regular unrolled decoder, employing fixed-point representations for numbers, with a comparable error-correction performance. A short systematic polar code is used as an illustration. All resulting unrolled decoders are shown to be capable of an information throughput of little under 10 Gbps in a 28 nm FD-SOI technology clocked in the vicinity of 1.4 GHz to 1.5 GHz. The best variant of our LUT-based decoders is shown to reduce the area requirements by 23% compared to the regular unrolled decoder while retaining a comparable error-correction performance.
Original language | English |
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Title of host publication | 2023 12th International Symposium on Topics in Coding, ISTC 2023 |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1-5 |
Number of pages | 5 |
ISBN (Electronic) | 979-8-3503-2611-6 |
DOIs | |
Publication status | Published - 10 Oct 2023 |
Event | 12th International Symposium on Topics in Coding, ISTC 2023 - Brest, France Duration: 4 Sept 2023 → 8 Sept 2023 |
Conference
Conference | 12th International Symposium on Topics in Coding, ISTC 2023 |
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Country/Territory | France |
City | Brest |
Period | 4/09/23 → 8/09/23 |
Funding
ACKNOWLEDGEMENT The authors would like to thank Marzieh Hashemipour Nazari (Eindhoven University of Technology) for providing the ASIC synthesis results. The work of Pascal Giard is supported by NSERC’s Discovery Grant #651824. The authors would like to thank Marzieh Hashemipour Nazari (Eindhoven University of Technology) for providing the ASIC synthesis results. The work of Pascal Giard is supported by NSERC s Discovery Grant #651824.
Funders | Funder number |
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Natural Sciences and Engineering Research Council of Canada | 651824 |
Eindhoven University of Technology |