Unipolar organic transistor circuits made robust by dual-gate technology

Kris Myny; Monique J. Beenhakkers; Nick A.J.M. van Aerle; Gerwin H. Gelinck; Jan Genoe; Wim Dehaene; Paul Heremans

doi:10.1109/JSSC.2011.2116490

Unipolar organic transistor circuits made robust by dual-gate technology

Kris Myny, Monique J. Beenhakkers, Nick A.J.M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans

Research output: Contribution to journal › Article › Academic › peer-review

100 Citations (Scopus)

Abstract

Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a V_T-control gate. Both zero-V_GS-load and diode-load logic are investigated. The noise margin of zero- V_GS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ∼0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- V _GS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

Original language	English
Article number	5733376
Pages (from-to)	1223-1230
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.2011.2116490
Publication status	Published - 1 May 2011
Externally published	Yes

Keywords

Dual-gate
organic circuits
organic RFID
organic transistor

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10.1109/JSSC.2011.2116490

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title = "Unipolar organic transistor circuits made robust by dual-gate technology",

abstract = "Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ∼0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- V GS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.",

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year = "2011",

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AU - van Aerle, Nick A.J.M.

AU - Gelinck, Gerwin H.

AU - Genoe, Jan

AU - Dehaene, Wim

AU - Heremans, Paul

PY - 2011/5/1

Y1 - 2011/5/1

N2 - Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ∼0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- V GS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

AB - Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ∼0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- V GS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

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Unipolar organic transistor circuits made robust by dual-gate technology

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Keywords

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