Understanding the impact of circuit-level inaccuracy on sensor network performance

Energy efficiency is of paramount importance in designing low-power wireless sensor nodes. Approximate computing is a new circuit-level technique for reducing power consumption. However, the gain in power by applying this technique is achieved at the cost of computational errors. The impact of such inaccuracies in the circuit level of a radio transceiver chip on the performance of Wireless Sensor Networks (WSNs) has not yet been explored. The applicability of such low-power chip design techniques depends on the overall energy gain and their impact on the network performance. In this paper, we analyze various inaccuracy fields in a radio chip, and quantify their impact on the network performance, in terms of packet latency, goodput, and energy per bit. The analysis is supported by extensive network simulations. The outcome can be used to investigate in which WSN application scenarios such power reduction techniques at circuit level can be applied, given the network performance and energy consumption requirements.