Ultra low energy domain specific instruction-set processor for on-line surveillance

D. Novo; A. Kritikakou; P. Raghavan; L. Van Der Perre; J. Huisken; F. Catthoor

doi:10.1109/SASP.2010.5521151

Ultra low energy domain specific instruction-set processor for on-line surveillance

D. Novo
, A. Kritikakou
, P. Raghavan
, L. Van Der Perre
, J. Huisken
, F. Catthoor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

Abstract

Many signal processing applications demand for highly energy efficient flexible implementations. In this paper, we propose a novel Domain Specific Instruction-set Processor (DSIP) architecture template which is tuned to deploy in the targeted domain of on-line surveillance. The architectur e, when implemented using a 40-nm CMOS standard cell library, executes a representative test vehicle with an energy efficiency of near ly 900 MOPS/mW including instruction and data memor ies. This is about 20 times higher than a state-of-the-ar t low power DSP architecture and less than a factor 2 below a heavily optimized ASIC realization for the same application benchmark.

Original language	English
Title of host publication	Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10
Publisher	IEEE Computer Society
Pages	30-35
Number of pages	6
ISBN (Print)	9781424479528
DOIs	https://doi.org/10.1109/SASP.2010.5521151
Publication status	Published - 24 Aug 2010
Externally published	Yes
Event	8th IEEE Symposium on Application Specific Processors, (SASP'10) - Anaheim, United States Duration: 13 Jun 2010 → 14 Jun 2010 https://pips4u.org/cfp_folder/sasp-2010

Conference

Conference	8th IEEE Symposium on Application Specific Processors, (SASP'10)
Abbreviated title	SASP'10
Country/Territory	United States
City	Anaheim
Period	13/06/10 → 14/06/10
Internet address	https://pips4u.org/cfp_folder/sasp-2010

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Domain specific instruction-set processor
Energy efficiency
Soft-SIMD

Access to Document

10.1109/SASP.2010.5521151

Cite this

@inproceedings{1537d98fd1c64a03a05c8117fde443a7,

title = "Ultra low energy domain specific instruction-set processor for on-line surveillance",

abstract = "Many signal processing applications demand for highly energy efficient flexible implementations. In this paper, we propose a novel Domain Specific Instruction-set Processor (DSIP) architecture template which is tuned to deploy in the targeted domain of on-line surveillance. The architectur e, when implemented using a 40-nm CMOS standard cell library, executes a representative test vehicle with an energy efficiency of near ly 900 MOPS/mW including instruction and data memor ies. This is about 20 times higher than a state-of-the-ar t low power DSP architecture and less than a factor 2 below a heavily optimized ASIC realization for the same application benchmark.",

keywords = "Domain specific instruction-set processor, Energy efficiency, Soft-SIMD",

author = "D. Novo and A. Kritikakou and P. Raghavan and \{Van Der Perre\}, L. and J. Huisken and F. Catthoor",

year = "2010",

month = aug,

day = "24",

doi = "10.1109/SASP.2010.5521151",

language = "English",

isbn = "9781424479528",

pages = "30--35",

booktitle = "Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10",

publisher = "IEEE Computer Society",

address = "United States",

note = "8th IEEE Symposium on Application Specific Processors, (SASP'10), SASP'10 ; Conference date: 13-06-2010 Through 14-06-2010",

url = "https://pips4u.org/cfp\_folder/sasp-2010",

}

Novo, D, Kritikakou, A, Raghavan, P, Van Der Perre, L, Huisken, J & Catthoor, F 2010, Ultra low energy domain specific instruction-set processor for on-line surveillance. in Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10., 5521151, IEEE Computer Society, pp. 30-35, 8th IEEE Symposium on Application Specific Processors, (SASP'10), Anaheim, California, United States, 13/06/10. https://doi.org/10.1109/SASP.2010.5521151

Ultra low energy domain specific instruction-set processor for on-line surveillance. / Novo, D.; Kritikakou, A.; Raghavan, P. et al.
Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10. IEEE Computer Society, 2010. p. 30-35 5521151.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Ultra low energy domain specific instruction-set processor for on-line surveillance

AU - Novo, D.

AU - Kritikakou, A.

AU - Raghavan, P.

AU - Van Der Perre, L.

AU - Huisken, J.

AU - Catthoor, F.

PY - 2010/8/24

Y1 - 2010/8/24

N2 - Many signal processing applications demand for highly energy efficient flexible implementations. In this paper, we propose a novel Domain Specific Instruction-set Processor (DSIP) architecture template which is tuned to deploy in the targeted domain of on-line surveillance. The architectur e, when implemented using a 40-nm CMOS standard cell library, executes a representative test vehicle with an energy efficiency of near ly 900 MOPS/mW including instruction and data memor ies. This is about 20 times higher than a state-of-the-ar t low power DSP architecture and less than a factor 2 below a heavily optimized ASIC realization for the same application benchmark.

AB - Many signal processing applications demand for highly energy efficient flexible implementations. In this paper, we propose a novel Domain Specific Instruction-set Processor (DSIP) architecture template which is tuned to deploy in the targeted domain of on-line surveillance. The architectur e, when implemented using a 40-nm CMOS standard cell library, executes a representative test vehicle with an energy efficiency of near ly 900 MOPS/mW including instruction and data memor ies. This is about 20 times higher than a state-of-the-ar t low power DSP architecture and less than a factor 2 below a heavily optimized ASIC realization for the same application benchmark.

KW - Domain specific instruction-set processor

KW - Energy efficiency

KW - Soft-SIMD

UR - https://www.scopus.com/pages/publications/77955745574

U2 - 10.1109/SASP.2010.5521151

DO - 10.1109/SASP.2010.5521151

M3 - Conference contribution

AN - SCOPUS:77955745574

SN - 9781424479528

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BT - Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10

PB - IEEE Computer Society

T2 - 8th IEEE Symposium on Application Specific Processors, (SASP'10)

Y2 - 13 June 2010 through 14 June 2010

ER -

Ultra low energy domain specific instruction-set processor for on-line surveillance

Abstract

Conference

UN SDGs

Keywords

Access to Document

Other files and links

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Cite this