Two-step interconnect testing of semiconductor dies

A method is provided for testing an interconnect (32) in a semiconductor die (30), the semiconductor die (30) having at its surface a plurality of electrical contact elements (Pad A, Pad B, Pad X, Pad Y), and comprising at least an interconnect-under-test (32) between a first electrical contact element (Pad A) and a second electrical contact element (Pad B), there being an electrical component (C) electrically coupled between the interconnect-under-test (32) and at least one third electrical contact element (Pad X, Pad Y). The method comprises testing a first signal path in the semiconductor die (30) for manufacturing defects, the first signal path comprising a first part of the interconnect-under-test (32) and a first deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad X), thus obtaining first test results; and testing a second signal path in the semiconductor die (30) for manufacturing defects, the second signal path comprising a second part of the interconnect-under-test (32) and a second deviation path from the interconnect-under-test (32) over the electrical component (C) to a third electrical contact element (Pad Y), thus obtaining second test results. The first and the second part of the interconnect-under-test together form the interconnect-under-test (32).