Two-step interconnect testing of semiconductor dies

J. Ryckaert (Inventor), E.J. Marinissen (Inventor), D. Linten (Inventor)

Research output: PatentPatent publication

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The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

Original languageEnglish
Patent numberUS2014300379
IPCH01L 21/ 66 A I
Priority date8/04/13
Publication statusPublished - 9 Oct 2014
Externally publishedYes


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