Twenty Years of Near/Sub-Threshold Design Trends and Enablement

Kamlesh Singh (Corresponding author), Jose Pineda de Gyvez

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (SciVal)


This tutorial paper surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this tutorial, we address the challenges of process variations and discuss the circuits and methods used over the years to minimize this impact. We discuss the advantages of standard-cell library design and provide a more involved pruning method to improve performance and robustness. Finally, we discuss the developments of the usually ignored power delivery techniques for near/sub-threshold circuits. We motivate the use of voltage stacking as a new power delivery technique for near/sub-threshold. This paper provides the basic enablement approaches for designing a chip operating in the near/sub-threshold region based on our experience.
Original languageEnglish
Article number9273082
Pages (from-to)5-11
Number of pages7
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number1
Early online date30 Nov 2020
Publication statusPublished - 1 Jan 2021


  • Body-biasing
  • Delays
  • Foundries
  • Libraries
  • Random access memory
  • Standards
  • Transistors
  • Voltage control
  • near/sub-threshold
  • power delivery
  • process variation
  • pruning
  • standard cell library
  • ultra-low power
  • ultra-low voltage.


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