An apparatus includes at least a first hardware part (AP1) and a second hardware part (AP2). Each of the first and second part include a respective processing element (CPU-1, CPU-2) and a respective signal connection to a respective memory element (MEM-1, MEM-2) for providing program code to the processing element of the respective part. The apparatus further includes a third hardware part (AP3) including at least one peripheral element acting as a source and/or destination of data. A fourth hardware part of the apparatus includes an I/O network (AP-4) for enabling communication between elements of the first and third part under control of first configuration data and for enabling communication between elements of the second and third part under control of distinct second configuration data.
|Publication status||Published - 7 Jun 2007|