Transition delay detector for interconnection test

S.K. Goel (Inventor), E.J. Marinissen (Inventor)

Research output: PatentPatent publication

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Abstract

PROBLEM TO BE SOLVED: To test for transition delay defects on inter-die interconnections in a structure including dies electrically connected to each other by inter-die interconnection.SOLUTION: An input port receives a test data value. A data storage element temporarily stores therein the test data value. For a first inter-die interconnection to be tested, a further inter-die interconnection is electrically connected to the first inter-die interconnection to form a feedback loop for transferring the test data value from the data storage element back to the data storage element. A data conditioner conditions the fed back test data value so that the fed back test data is distinguishable from the stored test data value. A clock pulse generator generates a delayed clock pulse. A selection logic circuit applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. The test data value stored in the data storage element is read out.

Original languageJapanese
Patent numberJP2014085348
IPCH01L 25/ 18 A I
Priority date19/10/12
Publication statusPublished - 12 May 2014
Externally publishedYes

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