Transition delay detector for interconnect test

S.K. Goel (Inventor), E.J. Marinissen (Inventor)

Research output: PatentPatent publication

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Abstract

The invention discloses a transition delay detector for interconnect test. A test circuitry (30) for testing for transition delay defects in inter-die interconnects in a structure comprising at least a first die (Die 1) and a second die (Die 2) electrically connected to one another by means of at least a first inter-die interconnect (interconnect 1), comprises an input port for receiving a test data value, a data storage element (33) for temporarily storing the test data value, at least for the first inter-die interconnect (interconnect 1) to be tested, and a further inter-die interconnect (interconnect 2) arranged for being electrically connected (32) to the first inter-die interconnect (interconnect 1) so as to form a feedback loop for transferring the test data value from the data storage element (33) back to the data storage element (33). The test circuitry further comprises a data conditioner, a clock pulse generator (36), selection logic, and readout means.

Original languageChinese
Patent numberCN103777090
IPCG01R 31/ 317 A I
Priority date19/10/12
Publication statusPublished - 7 May 2014
Externally publishedYes

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