Transformation-based exploration of data parallel architecture for customizable hardware : a JPEG encoder case study

R. Corvino, E. Diken, A. Gamatié, L. Jozwiak

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
96 Downloads (Pure)

Abstract

In this paper, we present a method for the design of MPSoCs for complex data-intensive applications. This method aims at a blend exploration of the communication, the memory system architecture and the computation resource parallelism. The proposed method is exemplified on a JPEG Encoder case study by describing all the design steps. Our method allows for a JPEG encoder implementation having a throughput increase of 84% and an increase of the achievable FPGA maximum frequency fmax of 64% with an area overhead of 6 with respect to a reference solution. Our method is also assessed with additional explorations of applications from different domains.
Original languageEnglish
Title of host publicationProceedings of the 15th Euromicro Conference on Digital System Design (DSD'12), 5-8 September 2012, Cesme, Izmir, Turkey
Place of PublicationBrussels
PublisherIEEE Computer Society
Pages774-781
ISBN (Print)978-1-4673-2498-4
DOIs
Publication statusPublished - 2012
Event15th Euromicro Conference on Digital System Design (DSD 2012) - Çeşme, Turkey
Duration: 5 Sep 20128 Sep 2012
Conference number: 15
http://www.univ-valenciennes.fr/congres/dsd2012/

Conference

Conference15th Euromicro Conference on Digital System Design (DSD 2012)
Abbreviated titleDSD 2012
CountryTurkey
CityÇeşme
Period5/09/128/09/12
OtherConference co-located with the 38th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2012)
Internet address

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